This invention relates to the fabrication of semiconductor integrated circuits (ICs). More particularly, the present invention relates to improved methods for etching a silicon layer in a plasma processing chamber to form deep openings having high aspect ratios.
In semiconductor IC fabrication, devices such as component transistors may be formed on a semiconductor wafer or substrate, which is typically made of silicon. Deep openings, which may have aspect ratios higher than 35:1, may be etched in the silicon for the purposes of, by way of example, storage, forming isolated capacitors or in MEM device applications. Openings having etch depths of about 3 .mu.m to about 10 .mu.m may be termed as deep openings, whereas openings having etch depths of more than about 10 .mu.m may be termed as ultra deep openings. These ranges are provided as a guide to explaining the invention, and are not intended to define any limitations to the invention. For example, it is assumed that a method for etching an ultra deep opening would be equally effective for etching a more shallow opening.
To facilitate this discussion, FIG. 1 shows the steps involved in a prior art method of etching deep openings that utilizes a prior art etching gas chemistry. This prior art method starts at 102 when a substrate is provided in a plasma processing chamber and begins with an initial breakthrough etch using a fluorine chemistry in 104, which may be, by way of example, CF4. This initial etch phase is followed by preparations for the main etch step, which starts at 106 by providing an SF.sub.6 /O.sub.2 /He etchant gas chemistry and striking a plasma using this gas chemistry in 108. Then the main etch starts in 110 by using the plasma to etch a deep opening in a silicon layer, for example, a trench having a depth of approximately 5.5 .mu.m. Once etching of the deep trench is accomplished, the process is complete as shown in 112.
FIG. 2 illustrates a cross-sectional view of an exemplary deep opening having an etch depth of approximately 5.5 .mu.m in a silicon layer with a masking layer over it that was etched using the prior art etching method presented in FIG. 1. A silicon layer 202, which has a masking layer 204 disposed over it, is etched to form a deep trench 206. Masking layer 204 may be a layer of conventional photoresist material, which may be patterned for etching, e.g., through exposure to ultraviolet rays. An etch rate of approximately 1.5 .mu.m/min is achieved. Deep trench 206, which was etched using the etching method described in FIG. 1, has a number of structural flaws, for example, bowed features 208 in the sidewalls as well as notch-like features 210, which resulted from undercutting of the hard mask.
Other issues that are not directly illustrated in FIG. 2 but may be encountered in the etching of deep trenches involve non-vertical etch profiles, low etch rates, inadequate etch depths, RIE lag, low TEOS/Si selectivity, critical dimension bias, and silicon nonuniformity. Some of these problems may not appear or become severe enough to pose difficulties until attempts are made to etch openings having greater etch depths and higher aspect ratios. It should be appreciated by those skilled in the art that the aforementioned issues will arise as rapid improvements in the industry call for the use of even deeper and narrower openings than are commonly used in today's state of the art technology.
In view of the foregoing, there are desired improved techniques of etching deep and narrow openings in a silicon layer while avoiding some or all of the numerous problems described above.